Realizarea unei surse de semnal digital programabilă

Cerinţe minimale:

• Generatorul de semnal va produce un semnal digital la unul din porturile FPGA. Semnalul generat va putea fi vizualizat cu osciloscopul sau analizorul logic.

• Sistemul va permite controlarea prin butoane şi switch-uri a frecvenţei şi factorului de umplere ale semnalului generat. Domeniul frecvenţei este 1Hz-10KHz iar domeniul factorului de umplere este 5%-95%.

• Sistem sincron, frecvenţa 50MHz.

• Reset asincron.

Prezentarea modulelor:

module debounce(signalinput,signaldebounced,clk,reset);

parameter width=10;

input signalinput;

input clk;

input reset;

output signaldebounced;

reg[width-1: 0] register;

always @(posedge clk or posedge reset)

if (reset) register<= 'b0;

else register <= {signalinput ,register[width-1:1]};

wire zero,unu;

assign zero = &register[width-1:0];

assign unu = ~|register[width-1:0];

reg signaldebounced;

always @(posedge clk or posedge reset)

begin

if (reset) signaldebounced <= 1'b0;

else if (unu) signaldebounced <= 1'b1;

else if (zero) signaldebounced <= 1'b0;

end

endmodule

module edgeDetectorModule (

clk,

reset,

signalIn,

signalPosEdgeOut,

signalNegEdgeOut,

signalEdgesOut

);

input clk;

input reset;

input signalIn;

output signalPosEdgeOut;

output signalNegEdgeOut;

output signalEdgesOut;

wire signalPosEdgeOut;

wire signalNegEdgeOut;

wire signalEdgesOut;

reg q;

always @( posedge clk or posedge reset )

begin

if ( reset ) q <= 1'b0;

else q <= signalIn;

end

assign signalPosEdgeOut = signalIn & !q;

assign signalNegEdgeOut = !signalIn & q;

assign signalEdgesOut = signalPosEdgeOut | signalNegEdgeOut;

endmodule

module frequencyGeneratorModule (

clk,

reset,

fEnable,

inc,

dec,

fact,

frequencyOut,

frequencyChangedOut

);

parameter length = 14;

input clk;

input reset;

input fEnable;

input inc;

input dec;

input [1:0] fact;

output[length-1:0] frequencyOut;

output frequencyChangedOut;

reg[length-1:0] frequencyOut;

wire frequencyChanged;

reg frequencyChangedOut;

wire finc;

wire fdec;

always @( posedge clk or posedge reset )

begin

if ( reset ) frequencyOut <= 1;

else

if ( fEnable )

if ( finc )

case ( fact )

0: frequencyOut <= frequencyOut + 'd1 ;

1: frequencyOut <= frequencyOut + 'd10 ;

2: frequencyOut <= frequencyOut + 'd100;

3: frequencyOut <= frequencyOut + 'd1000;

default : frequencyOut <= frequencyOut;

endcase

else

if ( fdec )

case ( fact )

0: frequencyOut <= frequencyOut - 'd1 ;

1: frequencyOut <= frequencyOut - 'd10 ;

2: frequencyOut <= frequencyOut - 'd100;

3: frequencyOut <= frequencyOut - 'd1000;

default : frequencyOut <= frequencyOut;

endcase

end